Pre Placement 3D Floor planning of 3D Modules Using Vertical Constraints For 3D IC'S

This project focuses on wire length reduction throughout the 3D floor layout stage. The 3D cell layout stage is part of the floor planning process. Previously, it was expected that the entire module would be placed on a single device layer. They don't consider how a module's cells may be dispersed across many device levels to reduce the cable length. Each of the device layers is assigned to one of the cells that make up a module (a 2D module is converted into a 3D module). To place cells in three dimensions, several constraints are used. The placement aware constraints are a set of constraints that determine whether a 2D module may be turned into a 3D module. The vertical alignment of identical submodules owing to the same planar placement requirement is referred to as vertical constraint. The size of the solution will be reduced as a result of this. A 3D floor design module packing method is proposed by the author. Calculating the wire length and taking into consideration the feasibility requirement, a smaller solution area is used to arrange the 3D cells in an initial set of floor layouts. After finding the best floor design, the modules are packed using a packing algorithm, and the technique is finished. A placement aware 3D floor design method is the name of the approach, which is developed in C++ and operates on Fedora Linux.

Keywords: AGC, CMOS, Error detector, VCO, PLL.